This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-353237, filed Nov. 20, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory and, more particularly, to a charge transfer sense amplifier for amplifying a small signal read out from a memory cell.
[A]
A current DRAM (Dynamic Random Access Memory) in which a memory cell is comprised of one transistor and one capacitor (1T1C cell) is mainstream.
In a DRAM having a memory cell arrays constituted by such memory cells arranged in the form of a matrix, for example, data read operation is executed in the following steps.
First of all, a bit line is precharged to set it at a precharge potential. The precharging of the bit line is then stopped, and the bit line is set in a floating state. Thereafter, a high potential is applied to a word line to turn on the transfer gate (transistor) of the memory cell.
In this case, since data is stored as the amount of charge stored in the capacitor in the memory cell, when the transfer gate of the memory cell is turned on, the amount of charge corresponding to a data value (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) stored in the memory cell is transferred from the memory cell to the bit line, and the charge is shared between the memory cell and the bit line.
At this time, the potential of the bit line varies from the precharge potential by a value corresponding to the amount of charge output from the memory cell. If, therefore, this change of the potential of the bit line is sensed and amplified by the sense amplifier, data can be read out from the memory cell.
A read scheme in which such a bit line and memory cell (capacitor) share charge will be referred to as a xe2x80x9ccharge-shared sense schemexe2x80x9d.
In actual data read operation, a pair of bit lines are used. For example, data is output to one of the pair of bit lines, and the other is maintained at the precharge potential (or reference potential). The small potential difference between the pair of bit lines is sensed by the sense amplifier and amplified.
A potential change xcex94Vb1 of a bit line due to cell data (the amount of charge) can be expressed by
xcex94Vb1=VBLH/2xc2x7(1+Cb/Cs)
where Cb is the bit line capacitance (all the capacitance produced in the bit line), Cs is the cell capacitance (the capacitance of the cell capacitor), VBLH is the xe2x80x9cH (High)xe2x80x9d level of the potential amplitude of the bit line, and VBLH/2 is the precharge potential of the bit line.
In this case, a ratio Cb/Cs of the bit line capacitance Cb, which serves as a parameter for determining the potential change xcex94Vb1, to the cell capacitance Cs is preferably minimized.
A 1T1C cell has been used from the days when a DRAM had a memory capacity of several kilobits to the present time when a DRAM at the gigabit level is under development. As a cell data read scheme as well, the above charge-shared sense scheme is generally used.
In the most advanced DRAM, a memory cell array or bit line is divided to decrease the length of each bit line so as to decrease the bit line capacitance Cb.
The cell capacitance (the capacitance of the storage node of the cell capacitor) Cs is increased by forming the cell capacitor into a 3D structure called a trench or stacked structure.
More specifically, in the trench structure, attempts have been made to increase the cell capacitance Cs by increasing the depth of a trench and increasing the aspect ratio of the trench. In the stack structure, attempts have been made to increase the cell capacitance Cs by devising the capacitor shape. There have been tendencies to decrease the Cb/Cs ratio in this manner.
This is because a decrease in the power supply voltage VBLH of a memory cell array associated with the problem of power consumption and a reduction in effective cell capacitance (a reduction in signal amount) due to leakage accompanying the prolongation of a refresh period have been compensated by a reduction in the Cb/Cs ratio.
[Problem 1]
As the size of a MOS transistor has recently been decreased extremely, the gate length has also been decreased very much. A threshold voltage Vth of the MOS transistor abruptly decreases due to the short channel effect as the gate length decreases. As the MOS transistor size decreases, variations in gate length in the manufacturing process lead to great variations in the threshold voltage Vth of the MOS transistor.
Note that a sense amplifier is generally laid out within the pitch of columns. For this reason, as the memory cell size greatly decreases, it is very difficult to reduce variations in the gate length of MOS transistors with a decrease in memory cell size.
[Problem 2]
For the above reasons, the sensing sensitivity of sense amplifiers (the minimum potential difference between a pair of bit lines which is required for a sense amplifier to appropriately amplify cell data) has hardly changed so far.
To accurately detect cell data by using a sense amplifier, therefore, a signal amount larger than a predetermined amount must be ensured.
Recently, however, as the memory cell size has decreased, the bit line capacitance Cb (especially, the capacitance produced between a pair of bit lines) has increased in a trench capacitor type memory cell. In a stack capacitor type memory cell (e.g., a COB (Capacitor Over Bitline) cell), the capacitance produced between a bit line and the storage node (especially, the contact area between a cell capacitor and a cell transistor) of a cell capacitor has increased.
Recently, therefore, with a decrease in memory cell size, it is very difficult to decrease the bit line capacitance Cb, and the bit line capacitance Cb is expected to gradually increase in the future.
It is expected that the cell capacitance Cs in, for example, a trench capacitance type memory cell, will gradually decrease with a decrease in memory cell size because the increase in the aspect ratio of a trench has approached to the process limit, and a decrease in the thickness of a capacitor insulating film is very difficult to attain in consideration of leak current and reliability. With the reduction in memory cell size, the power supply voltage (internal power supply voltage VBLH) of a memory cell array portion decreases. For this reason, it is difficult to keep the amount of signal read from a memory cell constant.
As described above, recently, as the memory cell size has decreased, it has been difficult to decrease the Cb/Cs ratio, and the Cb/Cs value has tended to increase. For this reason, the amount of signal read out from a memory cell decreases, and the potential difference between a pair of bit lines becomes less than the sensing sensitivity of the sense amplifier. As a consequence, the sense amplifier cannot sense cell data.
As for the increase in the cell capacitance Cs, a technique using a high dielectric constant film as a capacitor insulating film for a cell capacitor has been studied. It is expected that if this technique is put into practice, this problem will be left unsolved for the time being. It is, however, said that it will become impossible to read out data from a DRAM using 1T1C cells by the charge-share sense scheme in the near future.
As described above, in data read operation based on the charge-shared sense scheme, a bit line and a cell capacitor are electrically connected to each other to share charge. For this reason, with a reduction in memory cell size, as the cell capacitance Cs decreases and the bit line capacitance Cb increases, the amount of charge (signal amount) read out from the memory cell greatly decreases. As a result, the sense amplifier cannot detect cell data.
As precharge schemes for bit lines in data read operation, for example, the VBLH precharge scheme, VBLH/2 precharge scheme, and the like are known. In the VBLH/2 precharge scheme, as the voltage of the memory cell array portion decreases, the operation speed greatly decreases.
The fundamental problem that the amount of charge (signal amount) read out from a memory cell decreases with a reduction in memory cell size cannot be solved as long as the charge-shared sense scheme is used regardless of the type of precharge scheme (VBLH, VBLH/2, Vss, or the like).
[B]
A technique of solving the above fundamental problem by proposing a charge transfer sense scheme different from the above charge-shared sense scheme has been proposed by Heller et al. (L. G. Heller, D. P. Spampinato, and Y. L. Yao, xe2x80x9cHigh Sensitivity Charge-transfer Sense Amplifierxe2x80x9d, IEEE J. Solid-State Circuits, vol. SC-11, No. 5, pp. 596-601, 1976).
FIG. 1 is a circuit diagram for explaining the principle of the charge-transfer sense scheme proposed by Heller et al. FIG. 2 is a timing chart showing the operation of the circuit in FIG. 1.
An N-channel MOS transistor serving as a charge transfer gate is connected between a bit line BL and a sense amplitude node SA. A control signal VCTG is input to the gate of this MOS transistor. A P-channel MOS transistor is connected between the sense amplitude node SA and the VSAH node. A control signal PC is input to the gate of this MOS transistor.
At the beginning of data read operation, the control signal PC is set at a ground potential Vss, and hence the sense amplitude node SA is precharged to VSAH. In addition, since charge is supplied from the VSAH node to the bit line BL through the charge transfer transistor, the bit line BL is precharged to a value (VCTGxe2x88x92Vth) obtained by subtracting the threshold voltage Vth of the charge transfer transistor from the gate voltage VCTG of the charge transfer transistor (N-channel MOS transistor).
That is, the high potential VBLH of the potential amplitude of the bit line BL becomes VCTGxe2x88x92Vth. This potential VBLH becomes the potential of a storage node S when the cell data is xe2x80x9c1xe2x80x9d. Note that the low potential of the potential amplitude of the bit line BL is the ground potential Vss.
Thereafter, the control signal PC is set at a power supply potential VDD to cancel the precharged state of the sense amplitude node SA and bit line BL.
Assume that a selected word line WL is set at the read potential in this state. In this case, if the cell data in a memory cell connected to the selected word line WL is xe2x80x9c1xe2x80x9d (the potential of the storage node S is at VBLH), since there is no potential difference between the storage node S and the bit line BL, the potential of the bit line BL does not change (is maintained at VBLH).
If the cell data in the memory cell connected to the selected word line WL is xe2x80x9c0xe2x80x9d (the potential of the storage node S is at Vss), since charge moves from the bit line BL to the storage node S, the potential of the bit line BL drops. If the potential of the bit line BL becomes lower than VCTGxe2x88x92Vth, since the charge transfer transistor is turned on, charge moves from the sense amplifier node SA to the bit line BL.
Such movement of charge from the bit line BL to the storage node S and from the sense amplifier node SA to the bit line BL continues until the potential of the bit line BL becomes VCTGxe2x88x92Vth and reaches an equilibrium state again.
That is, the potential of the bit line BL before the application of potential to the selected word line WL is equal to that after the application of potential, and all the charge in the sense amplifier node SA is transferred to the bit line BL and storage node S. In this case, since a capacitance CSA of the sense amplifier node SA is much smaller than a capacitance CBL of the bit line BL, a change in the potential of the sense amplifier node SA in this charge transfer sense scheme is much larger than a change in the potential of the bit line BL in the charge-shared sense scheme.
If, therefore, a large change in the potential of the sense amplifier node SA is detected by a general sense amplifier, the substantial sensing sensitivity becomes very high.
In the charge transfer sense scheme according to Heller et al., however, the bit line BL must be precharged through a charge transfer transistor. This prolongs the precharge time and cycle time.
In addition, in the charge transfer sense scheme according to Heller et al., owing to the needs of the times, the VBLH precharge scheme of setting the precharge potential of the bit line BL at VBLH is used. For this reason, to generate a reference potential VREF required to detect cell data, {circle around (1)} a dummy cell having the same cell capacitance as that of a memory cell is prepared, and data (the amount of charge) intermediate between xe2x80x9c0xe2x80x9d data and xe2x80x9c1xe2x80x9d data must be written in this dummy cell, or {circle around (2)} a dummy cell having a cell capacitance xc2xd that of a memory cell is prepared, and xe2x80x9c1xe2x80x9d data must be written in this dummy cell.
At present, however, with a reduction in memory cell size, the cell capacitance Cs is realized by a complicated 3D structure (e.g., trench capacitor or stacked capacitor). This makes it difficult to accurately generate a dummy cell having a cell capacitance xc2xd that of a memory cell.
It is therefore be required that a dummy cell having the same cell capacitance as that of a memory cell be prepared, and data (the amount of charge) intermediate between xe2x80x9c0xe2x80x9d data and xe2x80x9c1xe2x80x9d data be written in this dummy cell ({circle around (1)}). In this case, for example, after one of bit lines is set at VBLH and the other bit line is set at Vss (full amplitude), an intermediate potential VREF is generated by equalizing the potentials of this pair of bit lines. This new cycle further prolongs the cycle time.
For the above reasons, the charge transfer sense scheme proposed by Heller et al. and a scheme as a combination of the charge transfer sense scheme and the VBLH precharge scheme have not been applied to DRAM products in spite of the fact that these schemes theoretically have high sensing sensitivity.
[C]
At present, with a reduction in memory cell size and a drop in the power supply voltage of a memory cell array portion, a data read failure in the charge-shared sense scheme+(VBLH/2) precharge scheme tends to become a reality.
Under the circumstances, attempts have been made to improve the sensing sensitivity and increase the read speed by combining the charge transfer sense scheme and the (VBLH/2) precharge scheme (e.g., M. Tsukude, S. Kuge, T. Fujio, and K. Arimoto, xe2x80x9cA1.2-to3.3-V Wide Voltage-Range/Low-Power DRAM with a Charge-Transfer Presensing Schemexe2x80x9d, IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1721-1727, Nov, 1997).
FIG. 3 is a circuit diagram for explaining the principle of data read by the charge transfer sense scheme+(VBLH/2) precharge scheme. FIG. 4 is a circuit diagram showing a concrete example of a sense amplifier and column select circuit. FIG. 5 is a timing chart showing the operation of the circuits shown in FIGS. 3 and 4.
The fundamental principle of this scheme is the same as that of the charge transfer sense scheme (FIGS. 1 and 2) proposed by Heller et al. This scheme differs from the scheme shown in FIGS. 1 and 2 in that {circle around (1)} bit lines and sense amplifier nodes are separately equalized and precharged, and {circle around (2)} the gate potential of a charge transfer transistor is controlled to change with time, instead of being fixed, in read operation.
In a precharge period, a control signal CT is at xe2x80x9cLxe2x80x9d level (Vss), and a charge transfer transistor is in the OFF state. In this state, since a control signal PC is at xe2x80x9cLxe2x80x9d level, the sense amplifier node SA and a sense amplifier node bSA are precharged to VSAH. In addition, since a control signal EQ is set at xe2x80x9cHxe2x80x9d level, the bit line BL and a bit line bBL are precharged to VBLH/2.
In a charge transfer/sense period, the control signal PC is set at xe2x80x9cHxe2x80x9d level and the control signal EQ is set at xe2x80x9cLxe2x80x9d level, and hence the precharged states of the sense amplifier nodes SA and bSA and bit lines BL and bBL are canceled.
Since the selected word line WL is set at VPP and the control signal CT is set at VCTG, the charge in the sense amplifier nodes SA and bSA is moved to the bit lines BL and bBL through the charge transfer transistors until the potentials of the bit lines BL and bBL are set at VCTGxe2x88x92Vth (where Vth is the threshold voltage of each charge transfer transistor). In addition, the charge in the bit lines BL and bBL is moved to the cell capacitor in accordance with the data in the memory cell (cell data).
If, for example, the cell data is xe2x80x9c0xe2x80x9d, since no charge is stored in the storage node of the cell capacitor, the charge in the bit lines BL and bBL is moved to the cell capacitor. If the cell data is xe2x80x9c1xe2x80x9d, since charge is stored in the storage node of the cell capacitor, the charge in the bit lines BL and bBL is not moved to the cell capacitor.
The amount of charge moved from the sense amplifier nodes SA and bSA to the bit lines BL and bBL varies depending on cell data.
In this case, the difference between the amount of charge moved from the sense amplifier nodes SA and bSA to the bit lines BL and bBL or the potential of the sense amplifier nodes SA and bSA after charge move when the cell data is xe2x80x9c0xe2x80x9d and the amount of charge moved from the sense amplifier nodes SA and bSA to the bit lines BL and bBL or the potential of the sense amplifier nodes SA and bSA after charge move when the cell data is xe2x80x9c1xe2x80x9d is equal to the value obtained by dividing the difference between the amount of charge stored in the cell capacitor of the memory cell storing xe2x80x9c0xe2x80x9d and the amount of charge stored in the cell capacitor of the memory cell storing xe2x80x9c1xe2x80x9d by the capacitance of the sense amplifier nodes SA and bSA.
That is, the potential difference obtained by the sense amplifier nodes SA and bSA using the charge transfer sense scheme is larger than the potential difference obtained by the sense amplifier nodes SA and bSA using the charge-shared sense scheme.
The potential difference obtained by the sense amplifier nodes SA and bSA is detected and amplified by, for example, a CMOS differential sense amplifier like the one shown in FIG. 4.
In this case, since the precharge level of the sense amplifier nodes SA and bSA is VSAH, sense amplifier activation signals SAN and SAP are also precharged to VSAH. In activating the sense amplifier, the sense amplifier activation signal SAN is set at Vss (ground potential), and the sense amplifier activation signal SAP is set at VBLH.
Note that the levels of the sense amplifier activation signals SAN and SAP in precharging the sense amplifier nodes SA and bSA may be set at VBLH and Vdd (internal power supply potential), respectively, under the condition that the sense transistor of a sense amplifier S/A is cut off.
In this case, since the potential of the sense amplifier nodes SA and bSA is higher than VBLH/2, the gate-source voltage of the sense transistor becomes high. This allows the sense amplifier to operate at high speed.
Subsequently, so-called restore operation is performed, i.e., the data read out from the memory cell is written in the memory cell again.
In the case shown in FIGS. 4 and 5, since an overall CMOS sense amplifier is arranged on the sense amplifier node side (the opposite side of a charge transfer transistor to a bit line), the control signal CT is set at a potential (e.g., VPP) higher than VCTG to let the pair of bit lines BL and bBL (or the storage node) go full swing (one of the pair of bit lines is set at VBLH, and the other at Vss).
After the restore operation, the sense amplifier nodes SA and bSA and the bit lines BL and bBL are precharged again to perform next data read.
In the charge transfer sense scheme+(VBLH/2) precharge scheme, even if it takes time more or less to do charge transfer, the time interval between the instant at which read operation is started and the instant at which the data amplified by the sense amplifier is output can be greatly shortened as a whole owing to a large read signal amount, a high gate-source voltage, and the like.
With a reduction in memory cell size, the main component of a bit line capacitance is the capacitance produced between adjacent bit lines. For this reason, in a memory cell having a trench capacitor structure, in particular, if the charge-shared sense scheme is used, the signal amount greatly decreases due to interference noise between the bit lines. In contrast to this, if the charge transfer sense scheme is used, since the potentials of a pair of bit lines after charge transfer become equal to each other, the influence of inter-bit interference noise is theoretically eliminated.
As described above, in the charge transfer sense scheme+(VBLH/2) precharge scheme, a sense amplifier can accurately sense cell data even if the cell capacitance decreases beyond the limit of the sensing sensitivity of a sense amplifier or the operating voltage of a memory cell array drops in the charge-shared sense scheme+(VBLH/2) precharge scheme.
As described above, according to the prior art, to cope with a reduction in memory cell size and a drop in power supply voltage, high sensing sensitivity is obtained by changing the data read scheme from the charge-shared sense scheme to the charge transfer sense scheme and increasing the signal amount read out from a memory cell to a sense amplifier node. Attempts have also been made to solve the problem of the read speed in the charge transfer sense scheme by using the charge transfer sense scheme+(VBLH/2) precharge scheme.
In the charge transfer sense scheme+(VBLH/2) precharge scheme as well, however, a characteristic mismatch due to manufacturing variations occurs in a pair of charge transfer transistors arranged for each pair of bit lines, as described in association with the charge-shared sense scheme (see [Problem 1] in section [A]).
A threshold voltage Vth mismatch between a pair of charge transfer transistors, in particular, becomes an offset, which is a potential difference, between the pair of bit lines BL and bBL after charge transfer. This offset increases in the sense amplifier nodes SA and bSA and hence will greatly degrade the sensing sensitivity of the sense amplifier.
A semiconductor memory according to an aspect of the present invention comprises a memory cell for storing data in the form of charge, a word line for selecting the memory cell, a bit line for reading out data from the memory cell, a sense amplifier which is connected to a sense amplifier node to amplify the data in the memory cell, a charge transfer transistor connected between the bit line and the sense amplifier node, and means for precharging the bit line and the sense amplifier node to different potentials.